1. Field of the Invention
The present invention generally relates to the manipulation of circuit components of a circuit design database and more particularly relates to a method and apparatus for selecting components.
2. Description of the Prior Art
The design process for all integrated circuits is composed of several discrete operations. Initially, the proposed functionality for a circuit is analyzed by one or more chip designers. These designers define the logical components of the circuit and their interactions by specifying the logic design using design capture tools. These design capture tools are commonly implemented in software executing on an engineering workstation, with well-known input devices being used to receive design information from the chip designer, and output devices, such as computer displays, being used to provide visual feedback of the design to the designer as it is being constructed. Such software is typically implemented as part of an electronic design automation (EDA) system. Specifically, the design entry operation involves generating a description of the logic design to be implemented on the circuit chip in an appropriate machine-readable form. Chip designers generally employ hierarchical design techniques to determine the appropriate selection and interconnection of logic and/or memory devices which will enable the chip to perform the desired function. These techniques involve describing the chip""s functionality at various levels of abstraction, ranging from the most general function performed by the chip to the precise functions performed by each logic and/or memory element on the chip.
A common method for specifying the integrated circuit design is the use of hardware description languages. This method allows a circuit designer to specify the circuit at the register transfer level (also known as a xe2x80x9cbehavior descriptionxe2x80x9d). Using this method, the circuit is defined in small building blocks. The names of the building blocks are specified by the circuit designer. Thus, they usually are logical names with specific functional meaning.
Encoding the design in a hardware description language (HDL) is a major design entry technique used to specify modern integrated circuits. Hardware description languages are specifically developed to aid a designer in describing a circuit. These languages often contain specific functions and syntax to allow complex hardware structures to be described in a compact and efficient way.
It is useful to distinguish between those components of an integrated circuit design called cells, provided by a silicon chip vendor as primitive cells (i.e., leaf candidates), and the user-defined hierarchy blocks built upon them. One way is to speak of a xe2x80x9ccell libraryxe2x80x9d vs. a xe2x80x9cdesign libraryxe2x80x9d as two separate libraries, both of which are available to subsequent designs. Alternatively, at least initially, a design library contains a cell library. A cell library is a database containing detailed specifications on the characteristics of each logical component available for use in a design. Initial cell library contents are usually provided by the chip vendor. The components in the cell library are identified by the generic description of the component type. For example, the term xe2x80x9cNANDxe2x80x9d for a NAND gate is its type description and distinguishes this component from others such as OR gates, flip-flops, multiplexors, and so on. A two-input NAND gate might be of type 2NAND. When a 2NAND component is specified as part of a given circuit design, it is given an instance name, to distinguish it from all other 2NAND gates used in the circuit. The instance name typically includes the instance names of all parent instances by concatenation when defining the instance in the context of the chip.
The user-defined blocks can then be used to design larger blocks of greater complexity. The user-defined blocks are added to the design library, which grows from the additions of new design modules as the design evolves. The top level of the design hierarchy may be a single block that defines the entire design, and the bottom layer of the hierarchy may consist of leaf cells, the cells (i.e., the logical components) that were originally provided in the cell library. Note that the hierarchy is typically structured as a special kind of a graph called a tree. This resulting data structure is called a detailed (or gate-level) description of the logic design.
The generation of the detailed description is often accomplished by logic design synthesis software for HDL entry. The logic design synthesis software generates a gate-level description of user-defined input and output logic, and also creates new gate-level logic to implement user-defined logical functions. Constituent parts of new gate-level logic created during each pass through the logic design synthesis software are given computer-generated component and net names. Each time the logic design synthesis software is executed for the integrated circuit design, the component and net names which are generated by the software, and not explicitly defined by the user, may change, depending on whether new logic has been added to or deleted from the integrated circuit design. Typically, the logic design synthesis software is executed many times during the integrated circuit design process, because errors may be detected during the simulation and testing phases of the design cycle and then fixed in the behavioral description.
The output of the design capture and synthesis tools is a logic design database which completely specifies the logical and functional relationships among the components of the design. Once the design has been converted into this form, it may be optimized by sending the logic design database to a logic optimizer tool implemented in software. The logic optimizer creates more efficient logic in terms of space, power or timing, and may remove logic from the design that is unnecessary. It is noted, however, that this action typically affects the component and net names generated by the logic synthesis tool.
It is also necessary to verify that the logic definition is correct and that the integrated circuit implements the function expected by the circuit designer. This verification is currently achieved by estimated timing and simulation software tools. The design undergoes design verification analysis in order to detect flaws in the design. The design is also analyzed by simulating the device resulting from the design to assess the functionality of the design. If errors are found or the resulting functionality is unacceptable, the designer modifies the behavior description as needed. These design iterations help to ensure that the design satisfies its requirements. As a result of each revision to the design, the logic design synthesis-generated component and net names may completely change. Further, the changes made by the logic optimizer may not be precisely known. Thus, the EDA tools downstream in the design process from the logic design synthesis software must be re-executed on the entire design.
After timing verification and functional simulation has been completed on the design, placement and routing of the design""s components is performed. These steps involve assigning components of the design to locations on the integrated circuit chip and interconnecting the components to form nets. This may be accomplished using automated place and route tools.
Because automatic placement tools may not yield an optimal design solution, particularly for high performance designs that have strict timing and physical requirements, circuit designers often manually place critical circuit objects (e.g. cells or regions) within the boundary of the integrated circuit. This may be accomplished by using a commercially available placement directive tool (also known as a floorplanning tool), typically implemented in software. The floorplanning tool may include a graphics terminal that provides the circuit designer with visual information pertaining to the circuit design. This information is typically contained in several different windows.
A floorplanning window may display a graphical representation of, for example, the die area of an integrated circuit, the placed objects and connectivity information. Similarly, a placed physical window may display the alphanumeric names of all placed cells and hierarchical regions. An un-placed physical window may display the alphanumeric names of all un-placed cells and hierarchical regions. A logic window may display a hierarchical tree graph of the circuit design.
During the placement process, the circuit designer may select the name of a desired object from the un-placed physical window displaying the un-placed objects. After this selection, the placement tool may retrieve the physical representation of the selected object, and the circuit designer may use the cursor to position the physical representation of the selected object within the floorplanning window. The placement tool may then move the alphanumeric name of the selected object from the un-placed physical window to the placed physical window to indicate the placement thereof.
To edit the placement of desired objects, the circuit designer typically selects the desired object from within the floorplanning window using a pointing device. The circuit designer may draw a rectangle around the desired objects to affect the selection. After selection, the circuit designer may instruct the placement tool to perform a desired editing function on the selected objects.
Some placement tools allow the circuit designer to select a desired level of hierarchy or region as the current working environment, or xe2x80x9ccontextxe2x80x9d. When the context is set, all of the objects existing at the next lower level in the circuit design hierarchy are displayed in one of the physical windows, thus making them available for placement or editing. These objects are called children objects of the selected context, and may include other hierarchical objects, including regions and/or cells. Thus, a context may include a mixture of regions and cells.
In this environment, circuit designers may perform preliminary placement by first placing high level regions. In some placement tools, the outer boundaries of the regions are appropriately sized to accommodate all underlying objects, even though all of the objects may not yet be placed. Thus, the circuit designer may rely on an automated placement tool to subsequently position the underlying objects within the boundary of the region. If more detailed placement is required because of timing, physical or other constraints, selected lower level regions or cells may be manually placed by the circuit designer.
These prior art placement tools suffer from a number of limitations, some of which are described below. First, while some placement tools allow operations to be performed on a user-defined group of objects using a pointing device within the placement tool (for example, selecting all objects within a certain area on the display device), they do not allow groups to be defined using level""s of logical hierarchy of the circuit design database. This provides a major limitation since many group operations are performed on a logical hierarchy basis. The ability to form groups based on the logical hierarchy can be particularly useful when multiple contexts overlap. In this situation, regions or cells within the overlapping contexts may be intermixed, and selecting only those regions or cells that correspond to a desired context can be difficult.
Furthermore, typical prior art placement tools do not allow a circuit designer to easily traverse the design hierarchy from within the floorplanning window, or easily select a desired context therein. In particular, if regions overlap, prior art tools typically cycled through the various overlapping regions until the desired region is finally located by the circuit designer. This could be a slow and tedious process because the regions may be large, including thousands of gates. Further, the selection process often involved loading the context information into local memory.
In addition to the above, typical prior art placement tools do not provide a mechanism for easily identifying selected objects for placement. In prior placement tools, when a context was loaded, the children cells appeared as a pseudo random list of names in a physical window. Since large contexts often contain thousands of regions and/or cells, the physical window provided little utility during the placement process. The circuit designer simply had to scroll through the often lengthy list of instances in an attempt to identify the desired object. It was often more efficient for the circuit designer to determine an instance name by cross-referencing an external listing so that the name could be entered manually prior to placement. Largely because of this tedious process, circuit designers often opted not to perform manual placement.
The present invention overcomes many of the disadvantages of the prior art by providing a method and apparatus for selecting components within a circuit design database. A number of features are provided for increasing the efficiency of the selection process. A first feature includes selecting only those objects that are in both a selected area and in a selected context. This feature may be particularly useful when multiple contexts overlap. In a preferred embodiment, this is accomplished by allowing only those cells that are associated with the selected context to be selected with a pointer device.
A second feature includes maneuvering through the circuit design hierarchy, and selecting cells or regions by using predetermined up and down hot-keys. This feature may allow a circuit designer to select a predetermined context by selecting a leaf cell known to be within the predetermined context by hitting a predetermined down hot-key, and then hitting an up hot-key to select the predetermined context. The up and down hot-key feature may allow a circuit designer to easily change the current context from within the floorplanning window to a different hierarchical level within the circuit design.
A third feature of the present invention includes sorting the un-placed objects by instance name, and manually selecting a desired object from the resulting sorted list. In prior placement tools, and as indicated above, when a context was loaded, the children objects appeared as a pseudo random list of names in a physical window. Since large contexts often contain thousands of instance names, the physical window provided little utility during the placement process. The circuit designer had to scroll through the often lengthy list of instances in an attempt to identify the desired object. It was often more efficient for the circuit designer to determine an instance name by cross-referencing an external listing so that the name could be entered manually prior to placement. Largely because of this tedious process, circuit designers often opted to not perform manual placement. In the present invention, the objects associated with a context may be sorted by instance or other name. This provides a readily understood order to the objects, thus enabling the circuit designer to quickly identify a desired object.
A fourth feature of the present invention includes sorting the un-placed objects by a corresponding net name, and manually selecting a desired object from the resulting sorted list. All of the un-placed objects are typically connected to at least one net within the design. For example, un-placed objects typically have an output which is coupled to a net. If the circuit design is generated by a synthesis tool, as described above, some of the net names will be computer generated. However, many synthesis tools retain the net names defined in the high level behavioral level description of the circuit design, particularly for vectored nets and the like. In these synthesis tools, the net names for each bit in a vectored net may have the same net name as a prefix with a bit number as a suffix (for example, NET1(0)). By sorting the instances according to the net names associated with a selected output, a circuit designer may easily select and place all objects associated with a vectored net. That is, all drivers of a vectored net may be sequentially listed in a physical window by sorting the instances by net name. This allows each of the instances to be easily placed in the floorplanning window.
A further advantage of both of the net name and instance name sorting features is that circuit designers may easily define object groups. This may allow user defined group operations to be more readily performed. For example, a circuit designer may place all drivers for a vectored net by: (1) performing an instance sort by net name; (2) selecting a first component from the group; (3) placing the first component; (4) specifying a direction for further group placement; and (5) automatically placing the remaining cells within the group in the specified direction (see for example, U.S. patent application Ser. No. 08/789,028, filed Jan. 27, 1997, which has been incorporated herein by reference). In the past, this simple operation typically required the circuit designer to manually find each instance name, either from some external printout or by panning through the unsorted list within a physical window, and individually place each object in the floorplanning window.